How long does the integration take?

Change one base URL in an OpenAI-compatible client, or install the Python or TypeScript SDK; the quickstart routes a first request in a few minutes.

Will this lock us into another vendor?

No. The router is Apache-2.0 open source, your provider keys stay yours, and the API is OpenAI-compatible, so leaving is a change of base URL.

What happens when a provider fails?

The router falls back to the next model your policy allows and records the fallback in the trace, so an outage costs a retry, not an incident.

questa-sim - Prompt - OpenSmartRoute

Name: questa-sim
Author: Aeeonn

Prompt file imported from Aeeonn/tilt-sand-fpga (.github/prompts/questa-sim.prompt.md). Copyright stays with the author.

Questa Simulation — Run & Report

Run a Questa Intel FPGA Starter Edition simulation for the specified testbench and report PASS/FAIL results.

Steps

Resolve the testbench name — accept either tb_foo or foo; always look for tb_<name>.sv.
Locate the do-script — find sim/scripts/do_<name>.do or sim/scripts/tb_<name>.do. If no script exists, stop and ask before improvising a compile/simulate sequence.
Locate the Questa installation — check for vsim / vlog in PATH or common install paths:
- C:\intelFPGA_lite\*\questa_fse\win64\
- C:\intelFPGA_lite\*\modelsim_ase\win64\
Run the simulation from the project root:
```
vsim -c -do "sim/scripts/do_<name>.do"
```
Use -c (command-line / no GUI) unless the user explicitly asks for the waveform GUI.
Parse the transcript (transcript in the project root) for:
- Lines matching PASS / FAIL / ERROR (case-insensitive)
- The final summary line: TB <module>: N/N PASS or *** FAIL ***
- Any $fatal, $error, or assertion failures
- Simulation time at finish

Present a result block:

Testbench : tb_<name>
Do-script : sim/scripts/do_<name>.do
Result    : PASS  (or FAIL — N failures)
Sim time  : X ns

If there are failures, list each one with its line/message from the transcript.

On failure:
- Show the failing check(s) and the mismatch (expected vs actual)
- Identify the likely RTL source location
- Propose a minimal fix candidate — do NOT implement it without user confirmation
Do not edit RTL as part of this prompt. Report only. If a fix is warranted, the user should invoke the FPGA HDL Steward agent for implementation.

Install questa-sim and it becomes one more candidate the router can pick - when it fits.

A listing is a routing target with a manifest: what it does, which domains it covers, what it costs and who publishes it. Once installed it sits beside your own models and tools, is scored like any other candidate for each request, and shows up in the trace when it wins. Ratings come from workspaces that installed it, one per account.

{ "prompt": "# Questa Simulation — Run & Report\r\n\r\nRun a Questa Intel FPGA Starter Edition simulation for the specified testbench and report PASS/FAIL results.\r\n\r\n## Steps\r\n\r\n1. **Resolve the testbench name** — accept either `tb_foo` or `foo`; always look for `tb_<name>.sv`.\r\n\r\n2. **Locate the do-script** — find `sim/scripts/do_<name>.do` or `sim/scripts/tb_<name>.do`. If no script exists, stop and ask before improvising a compile/simulate sequence.\r\n\r\n3. **Locate the Questa installation** — check for `vsim` / `vlog` in PATH or common install paths:\r\n - `C:\\intelFPGA_lite\\*\\questa_fse\\win64\\`\r\n - `C:\\intelFPGA_lite\\*\\modelsim_ase\\win64\\`\r\n\r\n4. **Run the simulation** from the project root:\r\n ```\r\n vsim -c -do \"sim/scripts/do_<name>.do\"\r\n ```\r\n Use `-c` (command-line / no GUI) unless the user explicitly asks for the waveform GUI.\r\n\r\n5. **Parse the transcript** (`transcript` in the project root) for:\r\n - Lines matching `PASS` / `FAIL` / `ERROR` (case-insensitive)\r\n - The final summary line: `TB <module>: N/N PASS` or `*** FAIL ***`\r\n - Any `$fatal`, `$error`, or assertion failures\r\n - Simulation time at finish\r\n\r\n6. **Present a result block**:\r\n\r\n ```\r\n Testbench : tb_<name>\r\n Do-script : sim/scripts/do_<name>.do\r\n Result : PASS (or FAIL — N failures)\r\n Sim time : X ns\r\n ```\r\n\r\n If there are failures, list each one with its line/message from the transcript.\r\n\r\n7. **On failure**:\r\n - Show the failing check(s) and the mismatch (expected vs actual)\r\n - Identify the likely RTL source location\r\n - Propose a minimal fix candidate — do NOT implement it without user confirmation\r\n\r\n8. **Do not edit RTL** as part of this prompt. Report only. If a fix is warranted, the user should invoke the FPGA HDL Steward agent for implementation.", "variables": [], "notes": "Run a Questa Intel FPGA simulation for a specific testbench and parse the PASS/FAIL results. Use when: running RTL unit tests, debugging a failing testbench, checking simulation transcript. Tools: execute, read, search. Arguments: Testbench module name (e.g. tb_vga_timing) — omit tb_ prefix if you prefer.", "metadata": { "source": { "provider": "github-prompts", "repository": "https://github.com/Aeeonn/tilt-sand-fpga", "path": ".github/prompts/questa-sim.prompt.md", "ref": "0d3b64c871918520a6d0d081be96559e6362dc06", "url": "https://github.com/Aeeonn/tilt-sand-fpga/blob/0d3b64c871918520a6d0d081be96559e6362dc06/.github/prompts/questa-sim.prompt.md", "key": "Aeeonn/tilt-sand-fpga/.github/prompts/questa-sim.prompt.md" } } }

questa-sim

About

Questa Simulation — Run & Report

Steps

Install questa-sim and it becomes one more candidate the router can pick - when it fits.

What it costs to adopt - in engineering time.

One base URL

No vendor lock-in

Failover built in

Use it

Manifest

Reviews