Instruction file imported from gabrielGAGRA/Laboratorio_de_Sistemas_Digitais-2 (
.cursor/rules/changes-checklist.mdc). Copyright stays with the author.
Feature Change Checklist
Post-change
- Quality gate: Run
python3 scripts/lint_verilog.py <files>. - Simulation gate: Execute the self-checking testbench with
iveriloguntil displays 0 errors. If checks fail or timing diverges, diagnose withpython3 scripts/vcd_trace.py <vcd>. - Rules / governance: When necessary only.
- Git: Only when requested by user.
- Adversarial review: Resolve required findings and re-run affected verification.
Decision Matrix
After finishing a task, evaluate downstream updates. Open a file ONLY when a trigger below matches.
| You Changed | Evaluate |
|---|---|
Submodule or Datapath (*_fd.v or primitive) |
Check top-level instantiation connections and parent testbench |
Control Unit FSM (*_uc.v) |
Check state encoding constants, latch prevention defaults, and FSM testbench |
Top-level module (Laboratórios/EXPx/*/*.v) |
Verify pin mapping against DE0-CV pinouts, run full top-level testbench |
Testbench (tb_*.v or *_tb.v) |
Ensure self-checking logic, termination via $finish, and check waveform dump flags |
Promoting from Planejamento/ to Relatório/ |
Run full linter and regression test suite across all modules in the experiment |